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rev 0.1 / apr ? 01 the gm71v(s)16163c/cl is the new generation dynamic ram organized 1,048,576 x 16 bit. gm71v(s)16163c/cl has realized higher density, higher performance and various functions by utilizing advanced cmos process technology. the gm71v(s)16163c/cl offers extended data out(edo) mode as a high speed access mode. multplexed address inputs permit the gm71v(s)16163c/cl to be packaged in standard 400 mil 42pin plastic soj, and standard 400mil 44(50)pin plastic tsop ii. the package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. description features * 1,048,576 words x 16 bit organization * extended data out mode capability * single power supply (3.3v+/-0.3v) * fast access time & cycle time ( unit: ns) pin configuration 1,048,576 words x 16 bit cmos dynamic ram gm71vs16163cl gm71v(s)16163c/cl-5 gm71v(s)16163c/cl-6 gm71v(s)16163c/cl-7 t rac t cac t rc t hpc 50 60 13 15 84 104 20 25 70 18 124 30 gm71v(s)16163c/cl-8 80 20 144 35 * low power active : 396/360/324/288mw (max) standby : 7.2mw (max) 0.83 mw (l-series : max) * ras only refresh, cas before ras refresh, hidden refresh capability * all inputs and outputs ttl compatible * 4096 refresh cycles/64ms * 4096 refresh cycles/128ms (l-series) * self refresh operation (l-version) * battery back up operation (l-series) * 2 cas byte control ( top view) v cc i/o0 i/o1 i/o2 i/o3 1 2 3 4 5 i/o4 i/o5 i/o6 i/o7 nc 7 8 9 10 11 v cc 6 nc we ras 12 13 14 a11 a10 a0 15 16 17 a1 a2 a3 18 19 20 v ss i/o15 i/o14 i/o13 i/o12 38 39 40 41 42 i/o11 i/o10 i/o9 i/o8 nc 32 33 34 35 36 v ss 37 lcas ucas oe 29 30 31 a9 a8 a7 26 27 28 a6 a5 a4 23 24 25 v cc 21 v ss 22 11 1 2 3 4 5 7 8 9 10 6 15 16 17 18 19 20 21 22 23 24 25 42 43 44 45 46 40 41 33 30 31 32 27 28 29 26 34 35 36 47 48 49 50 nc nc nc nc i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 v cc nc we ras a11 a10 a0 a1 v ss i/o15 i/o14 i/o13 i/o12 i/o11 i/o10 i/o9 i/o8 v ss lcas ucas oe a8 a7 a6 a5 a4 v cc v cc a2 a3 v ss a9 42 soj 44(50) tsop ii GM71V16163C
rev 0.1 / apr ? 01 pin description pin function pin function a0-a11 a0-a11 i/o0-i/o15 ras we v cc v ss nc address inputs refresh address inputs data-in/out row address strobe write enable power (+3.3v) ground no connection ordering information cas column address strobe oe output enable absolute maximum ratings* type no. access time package gm71v(s)16163cj/clj -5 gm71v(s)16163cj/clj -6 gm71v(s)16163cj/clj -7 gm71v(s)16163cj/clj -8 50 ns 60ns 70ns 80ns 400 mil 42 pin plastic soj 50 ns 60ns 70ns 80ns 400 mil 44(50) pin plastic tsop ii (normal type) gm71v(s)16163ct/clt -5 gm71v(s)16163ct/clt -6 gm71v(s)16163ct/clt -7 gm71v(s)16163ct/clt -8 * note: all voltage referred to vss . symbol parameter rating unit t a t stg v t v cc i out 0 ~ 70 -55 ~ 125 -0.5 ~ vcc +0.5 (<=4.6v(max)) -0.5 ~ 4.6 50 ambient temperature under bias storage temperature voltage on any pin relative to v ss supply voltage relative to v ss short circuit output current v v ma p t 1.0 power dissipation w recommended dc operating conditions (t a = 0 ~ 70c) symbol parameter unit v cc v ih v il supply voltage input high voltage input low voltage v v v max 3.6 v cc + 0.3 0.8 typ 3.3 - - min 3.0 2.0 -0.3 c c gm71vs16163cl GM71V16163C
rev 0.1 / apr ? 01 truth table notes: 1. h: high (inactive) l: low(active) d: h or l 2. t wcs >= 0ns early write cycle t wcs < 0ns delayed write cycle 3. mode is determined by the or fuction of the ucas and lcas. (mode is set by earliest of ucas and lcas active edge and reset by the latest of ucas and lcas inactive edgs .) however write operation and output hiz control are done independently by each uacs,lcas. ex. if ras = h to l, ucas = h, lcas = l, then cas-before-ras refresh cycle is selected. ras lcas ucas we oe h l l l d h l h d h h l d h h h d d l l output open valid valid valid lower byte upper byte word operation standby las-only refresh cycle read cycle l l l l l l h l h early write cycle l h l l h open open open l l l l undefined delayed write cycle l l l h h h to l l cbr refresh or self refresh (l-series) h to l h l h to l l l notes 1,3 1,3 1,3 1,3 1,3 1,2,3 1,2,3 1,3 lower byte upper byte word lower byte upper byte word lower byte upper byte word undefined undefined open open open open open valid valid valid word word word word read-modify -write cycle read cycle (output disabled) d d h to l h to l h to l l l l l l l l h l l l l h d d l h h h h l d d d d d d l to h l to h l to h l l l l gm71vs16163cl GM71V16163C
rev 0.1 / apr ? 01 dc electrical characteristics (v cc = 3.3v+/-0.3v, vss = 0v, t a = 0 ~ 70c) symbol parameter note v oh v ol output level output "h" level voltage (i out = -2 ma ) unit v v max v cc 0.4 min 2.4 0 output level output "l" level voltage (i out = 2 ma ) i cc1 ma 110 - operating current average power supply operating current (ras, cas cycling : t rc = t rc min) 50 ns 60 ns 70 ns 100 90 - - 1, 2 i cc2 ma standby current (ttl) power supply standby current (ras, cas = v ih , d out = high-z) 2 - i cc3 ma ras only refresh current average power supply current ras only refresh mode ( t rc = t rc min) 2 i cc4 ma 1, 3 - i cc5 ma standby current (cmos) power supply standby current (ras, cas > v cc - 0.2v, dout = high-z) 1 - i cc6 ma cas-before-ras refresh current ( t rc = t rc min) 110 - 50 ns 60 ns 70 ns - - i cc7 battery back up operating current(standby with cbr ref.) (cbr refresh, t rc =31.3us , t ras <= 0.3 us, d out = high-z,cmos interface) 400 - 150 - standby current ras = v ih cas = v il d out = enable 5 - 1 i li ua 10 -10 i lo ua 10 -10 input leakage current any input (0v <= v in <= 4.6v) output leakage current (d out is disabled, 0v <= v out <= 4. 6v) note: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less while cas = v ih . 4. cas = l ( <= 0.2v) while ras = l ( <= 0.2v). 5. l - series. ma 4,5 edo page mode current average power supply current edo page mode ( t hpc = t hpc min) 100 90 ua 5 ua 80 ns 80 80 ns 80 110 - 50 ns 60 ns 70 ns 100 90 - - 80 ns 80 - - 105 - 50 ns 60 ns 70 ns 95 85 - - 80 ns 75 i cc8 i cc9 ua self-refresh mode current (ras, cas<=0.2v , d out = high-z, cmos interface) 250 - 5 gm71vs16163cl GM71V16163C
rev 0.1 / apr ? 01 read, write, read-modify-write and refresh cycles (common parameters) symbol parameter note max unit min max min max min t rc random read or write cycle time 84 - 104 - 124 - t rp ras precharge time 30 - 40 - 50 - t ras ras pulse width 50 10,000 60 10,000 70 10,000 t cas cas pulse width 8 10,000 10,000 10,000 10 13 t asr row address set up time 0 - - - 0 0 t rah row address hold time 8 - - - 10 10 t asc column address set-up time 0 - - - 0 0 t cah column address hold time 8 - - - 10 13 t rcd ras to cas delay time 12 37 45 52 14 14 3 t rad ras to column address delay time 10 25 30 35 12 12 4 t rsh ras hold time 10 - - - 13 13 t csh cas hold time 35 - - - 40 45 t crp cas to ras precharge time 5 - - - 5 5 t t transitiontime (rise and fall) 2 50 50 50 2 2 7 capacitance (v cc = 3.3v +/- 0.3v, t a = 25 c ) symbol parameter note c i1 c i2 c i/o input capacitance (address) input capacitance (clocks) output capacitance (data-in/out) 1 1 1, 2 unit pf max 5 7 7 min - - - note: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. cas = v ih to disable d out . ac characteristics (v cc = 3.3v+/-0.3v, t a = 0 ~ + 70c, vss = 0v) note 1, 2, 18, 19, 20 t dzo oe delay time from d in 0 - - - 0 0 t dzc cas delay time from d in 0 - - - 0 0 gm71v(s)16163 c/cl-5 oe to d in delay time 13 - - - 15 18 5 6 6 t cp cas precharge time 8 - 10 - 13 - t oed test conditions input rise and fall times : 2 ns output load : 1ttl gate + c l (100 pf ) input timing reference levels : 0.8v, 2.0v (including scope and jig) output timing reference levels : 0.8v, 2.0v gm71v(s)16163 c/cl-6 gm71v(s)16163 c/cl-7 max min 144 - 60 - 80 10,000 10,000 15 - 0 - 10 - 0 - 15 60 20 40 15 - 18 - 50 - 5 50 2 - 0 - 0 - 20 15 - gm71v(s)16163 c/cl-8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pf pf 21 21 22 23 gm71vs16163cl GM71V16163C
rev 0.1 / apr ? 01 read cycle symbol parameter note max unit min max min max min t rac access time from ras - 60 - 70 - 80 t cac access time from cas - 15 - 18 - 20 t aa access time from address - 30 - 35 - 40 t rcs read command setup time 0 - 0 - 0 - t rch read command hold time to cas 0 - - - 0 0 8,9 9,10,17 9,11,17 - 15 - 18 - 20 9 12,22 access time from oe gm71v(s)16163 c/cl-6 t oea gm71v(s)16163 c/cl-7 gm71v(s)16163 c/cl-8 t rrh read command hold time to ras 5 - - - 5 5 12 t ral column address to ras lead time 30 - - - 35 40 t off output buffer turn-off time 15 15 15 13,27 - - - t cal column address to cas lead time 18 - - - 23 28 t clz cas to output in low-z 0 - - - 0 0 t oez output buffer turn-off time to oe 15 15 15 13 - - - t oh output data hold time 3 - - - 3 3 t oho output data hold time from oe 3 - - - 3 3 t cdd cas to d in delay time 15 - - - 18 20 5 t rchr t ohr t ofr t wez t wed t rod read command hold time from ras 60 70 80 output data hold time from ras 3 3 3 output buffer turn off to ras output buffer turn off to we we to d in deray time ras to d in delay time 15 15 15 15 15 18 18 20 20 - - - - - - - - - - - - - - - - - - max min - 50 - 13 - 25 0 - 0 - - 13 gm71v(s)16163 c/cl-5 5 - 25 - 13 - 15 - 0 - 13 - 3 - 3 - 13 - 50 3 13 13 13 - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 15 15 15 21 27 27 27 gm71vs16163cl GM71V16163C
rev 0.1 / apr ? 01 write cycle symol parameter note max unit min max min max min t wcs write command setup time 0 - 0 - 0 - t wch write command hold time 10 - 13 - 15 - t wp write command pulse width 10 - 10 - 10 - t rwl write command to ras lead time 10 - 13 - 15 - t cwl write command to cas lead time 10 - - - 13 15 t ds data-in setup time 0 - - - 0 0 t dh data-in hold time 10 - - - 13 15 15,23 15,23 14,21 gm71v(s)16163 c/cl-6 gm71v(s)16163 c/cl-7 gm71v(s)16163 c/cl-8 read- modify-write cycle symbol parameter note max unit min max min max min t rwc read-modify-write cycle time 136 - 161 - 185 - t rwd ras to we delay time 79 - 92 - 104 - t cwd cas to we delay time 34 - 40 - 44 - t awd column address to we delay time 49 - 57 - 64 - 14 14 14 t oeh oe hold time from we 15 - 18 - 20 - gm71v(s)16163 c/cl-6 gm71v(s)16163 c/cl-7 gm71v(s)16163 c/cl-8 ns min 0 - 8 - 8 - - - 0 - - max gm71v(s)16163 c/cl-5 8 8 8 ns ns ns ns ns ns ns ns ns ns ns min 111 - 67 - 30 - 42 - 13 - max gm71v(s)16163 c/cl-5 21 23 gm71vs16163cl GM71V16163C
rev 0.1 / apr ? 01 symbol parameter note max unit min max min max min t hpc 25 - 30 - 35 - t rasp t acp access time from cas precharge 35 - 40 - 45 t rhcp ras hold time from cas precharge 9,17,22 - - - 16 edo page mode ras pulse width 100,000 100,000 100,000 - - - 35 40 45 gm71v(s)16163 c/cl-6 - gm71v(s)16163 c/cl-7 gm71v(s)16163 c/cl-8 edo page mode cycle edo page mode cycle time refresh cycle symbol parameter note max unit min max min max min t csr cas setup time (cas-before-ras refresh cycle) 5 - 5 - 5 - ns t chr cas hold time (cas-before-ras refresh cycle) 10 - 10 - 10 - ns t rpc ras precharge to cas hold time 5 - 5 - 5 - ns gm71v(s)16163 c/cl-6 gm71v(s)16163 c/cl-7 gm71v(s)16163 c/cl-8 t wrp we setup time (cas-before-ras refresh cycle) 0 - 0 - 0 - ns t wrh we hold time (cas-before-ras refresh cycle) 10 - 10 - 10 - ns 25 t doh t col t cop t rchp output data hold time from cas low 3 3 3 - - - - - - - - 9 cas hold time referred oe 10 13 15 cas to oe setup time 5 5 5 read command hold time from cas precharge 35 40 45 ns ns ns ns ns ns ns ns min 20 - 30 - - - gm71v(s)16163 c/cl-5 3 - - - - 5 30 max 100,000 8 min 5 - 8 - 5 - gm71v(s)16163 c/cl-5 0 - 10 - max 21 22 21 30 gm71vs16163cl GM71V16163C
rev 0.1 / apr ? 01 edo page mode read-modify-write cycle symbol parameter note max unit min max min max min t hprwc edo page mode read-modify-write cycle time 68 - 79 - 88 - ns t cpw we delay time from cas precharge 54 - 62 - 69 - ns 14,22 gm71v(s)16163 c/cl-6 gm71v(s)16163 c/cl-7 gm71v(s)16163 c/cl-8 refresh symbol parameter note max unit min max min max min t ref refresh period 64 - - 64 - ms t ref refresh period (l -series) 128 - 128 - 128 - ms gm71v(s)16163 c/cl-6 gm71v(s)16163 c/cl-7 gm71v(s)16163 c/cl-8 64 4096 cycles 4096 cycles max min 57 - 45 - gm71v(s)16163 c/cl-5 max min 64 - 128 - gm71v(s)16163 c/cl-5 self refresh mode ( l-version ) symbol parameter note max unit min max min max min t rass ras pulse width(self-refresh) 100 - 100 - 100 - t rps ras precharge time(self-refresh) 110 - 130 - 150 - ns t chs cas hold time(self-refresh) -50 - -50 - -50 - ns gm71v(s)16163 c/cl-6 gm71v(s)16163 c/cl-7 gm71v(s)16163 c/cl-8 us max min 100 - 90 - -50 - gm71v(s)16163 c/cl-5 29 gm71vs16163cl GM71V16163C
rev 0.1 / apr ? 01 notes: 1. ac measurements assume t t = 5ns. 2. an intial pause of 200us is required after power up followd by a minimum of eight initialization cycles(any combination of cycles containing ras-only refresh or cas-before-ras refresh). if the internal refresh counter is used, a minimum of eight cas-before-ras refresh cycles are required. 3. operation with the t rcd (max)limit insures that t rac (max)can be met, t rcd (max)is specified as a reference point only; if t rcd >= t rad (max) + t aa (max) - t cac (max), then access time is controlled exclusively by t cac . 4. operation with the t rad (max) limit insures that t rac (max)can be met, t rad (max)is specified as a reference point only; if t rad is greater than the specified t rad (max)limit, then access time is controlled exclusively by t aa . 5. either t oed or t cdd must be satisfied. 6. either t dzo or t dzc must be satisfied. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). 8. assumes that t rcd <= t rcd (max) and t rad <= t rad (max). if t rcd ot t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 9. measured with a load circuit equivalent to 1 ttl load and 100pf. 10. assumes that t rcd >= t rcd (max) and t rcd + t cac (max) >= t rad + t aa (max). 11. assumes that t rad >= t rad (max) and t rcd + t cac (max) <= t rad + t aa (max). 12. either t rch or t rrh must be satisfied for a read cycles. 13. t off (max) and t oez (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t wcs , t rwd , t cwd , t awd and t cpw are not restrictive operationg parameters. they are included in the data sheet as electrical characteristics only; if t wcs >= t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedence ) throughout the entire cycle ; if t rwd >= t rwd (min), t cwd >= t cwd (min), and t awd >= t awd (min), or t cwd >= t cwd (min), t awd >= t awd (min) and t cpw >= t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of data out (at access time)is indeterminate. 15. these parameters are referred to ucas and lcas leading edge in early write cycles and to we leading edge in delayed write or read-modify-write cycles. 16. t rasp defines ras pulse width in edo page mode cycles. 17. access time is determined by the longest among t aa , t cac ,and t acp . 18. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. after ras is reset, if t oeh >= t cwl , the i/o pin will remain open circuit (high impedence ); if t oeh < t cwl , invalid data will be out at each i/o. 19. when both ucas and lcas go low at the same time, all 16-bit data are written into the device. ucas and lcas cannot be staggered within the same write/read cycles. 20. all the v cc and v ss pins shall be supplied with the same voltages. gm71vs16163cl GM71V16163C
rev 0.1 / apr ? 01 21. t asc , t cah , t rcs , t wcs , t wch , t csr and t rpc are determined by the earlier falling edge of ucas or lcas. 22. t crp , t chr , t rch , t acp and t cpw are determned by the later rising edge of ucas or lcas. 23. t cwl , t dh , t ds and t csh should be satisfied by both ucas and lcas. 24. t cp is determined by that time the both ucas and lcas are high. 25. when output buffers are enabled once, sustain the low impedence state until valid data is obtained. when output buffer is turned on and off within a very short time, generally it causes large v cc /v ss line noise, which causes to degrade v ih min/v il max level. 26. please do not use t rass timing, 10us <= t rass <= 100us. during this period, the device is in transition state from normal operation mode to self refresh mode. if t rass >= 100us, then ras precharge time should use t rps instead of t rp . 27. if you use distributed cbr refresh within 15.6us inteval in normal read/write cycle, cbr refresh should be executed within 15.6us immediately after exiting from and before entering into self refresh mode. 28. if you use ras only refresh or cbr burst refresh mode in normal read/write cycle,4096 or 1024 cycles of distributed cbr refresh with 15.6us interval should be executed within 64 or 16ms immediately after exiting from and before entering into the self refresh mode. 29. repetitive self refresh mode without refreshing all memory is not allowed. once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 30. h or l (h: v ih (min) <= v in <= v ih (max), l: v il (min) <= v in <= v il (max)) gm71vs16163cl GM71V16163C
rev 0.1 / apr ? 01 notes concerning 2cas control please do not separate the ucas / lcas operation timing intentionally. however skew between ucas / lcas are allowed under the following conditions. 1. each of the ucas / lcas should satisfy the timing specifications individually. 2. different operation mode for upper/lower byte is not allowed;such as following. ras ucas lcas we delayed write early write 3. closely separated upper/lower byte control is not allowed. however when the condition ( t cp < t ul )is satisfied,edo page mode can be performed. ras ucas lcas t ul 4. byte control operation by remaining ucas or lcas high is guaranteed. gm71vs16163cl GM71V16163C
rev 0.1 / apr ? 01 package dimensions unit : inches (mm) 0.017(0.45) max 0.011(0.30) min typ 0.031(0.80 ) 0.005(0.15) max 0.001(0.05) min 0.829(21.08) max 0.819(20.82) min 0.405(10.29) max 1.072(27.23) max 0.395(10.03) min 0.435(11.05) min 0.445(11.30) max 0.148(3.75) max 0.128(3.25) min typ 0.050(1.27) 0.360(9.15) min 0.380(9.65) max 0.025(0.64) min 0.093(2.38) min 0.405(10.29) max 0.020(0.50) max 0.015(0.38) min 0.026(0.66) min 1.058(26.89) min 42 soj 44(50) tsop (type ii) 0.024(0.60) max 0.016(0.40) min 0.445(11.56) min 0.471(11.96) max 0.008(0.21) max 0~5 o 0.004(0.12) min 0.394(10.03) min 0.032(0.81) max 0.047(1.20) max 0.037(0.95) min 0.041(1.05) max gm71vs16163cl GM71V16163C

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